The present disclosure relates to a lateral bipolar transistor (BJT) structure, and particularly to a lateral bipolar junction transistor including a SiGe base and located on an semiconductor-on-insulator (SOI) substrate and methods of manufacturing the same.
The parasitic capacitance between the extrinsic base, the emitter, and/or the collector is a performance-limiting factor for a bipolar junction transistor. The parasitic capacitance reduces the switching speed of the bipolar junction transistor. The noise generated at the periphery of the base is another performance-limiting factor for a bipolar junction transistor. Typically, charge carriers can be temporarily captured at an interface between the base and a surrounding dielectric material, and emitted at a subsequent time to introduce electrical noise in the signal. In order to provide signal amplification with high fidelity, such noise must be suppressed to a minimum level. Yet another performance-limiting factor for a bipolar junction transistor is the maximum current density that the transistor can handle without speed degradation. Further, practical issues of manufacturability, i.e., lower processing cost, short processing time, and high process yield, must be addressed in order to provide a high-performance bipolar junction transistor that can be commercially manufactured.
While many types of bipolar junction transistors have been proposed in the prior art, most fail to simultaneously address the above issues, let alone providing a satisfactory solution addressing them.